Maxelweb/cps-lab-exercises-2021
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add lab1 and lab2 exercises

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Mariano Sciacco
2021-11-19 10:36:17 +01:00
parent 4d2c26287f
commit 15e2cad2c9
12 changed files with 511 additions and 2 deletions
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lab1/README.md Normal file
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# CPS Lab 1 Exercise (2021-10-27)
- Mariano Sciacco
- Davide Farinelli

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lab1/delay_inverter.smv Normal file
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MODULE delay(input)
-- Model of the delay component
VAR
x : boolean;
ASSIGN
init(x) := FALSE;
next(x) := input;
DEFINE
out := x;
MODULE relay(input)
-- Model of the relay
DEFINE
out := input;
MODULE inverter(input)
-- Model of the inverter
DEFINE
out := !input;
MODULE main
-- Composition of delay and inverter
VAR
del : delay(inv.out);
inv : inverter(del.out);
INVARSPEC inv.out = !del.out;

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lab1/ex_lab01.pdf Normal file
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lab1/railroad.smv Normal file
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MODULE train(signal)
-- Model of the train
VAR
mode : {away, wait, bridge};
out : {none, arrive, leave};
ASSIGN
init(mode) := away;
out := case
mode = away : {none, arrive};
mode = bridge : {none, leave};
TRUE : none;
esac;
next(mode) := case
mode = away & out = arrive : wait;
mode = wait & signal = green : bridge;
mode = bridge & out = leave : away;
TRUE : mode;
esac;
MODULE controller(out_w, out_e)
-- First model of the controller
VAR
west : {green, red};
east : {green, red};
nearw : {0, 1};
neare : {0, 1};
ASSIGN
init(west) := red;
init(east) := red;
init(nearw) := 0;
init(neare) := 0;
next(neare) := case
out_e = arrive : 1;
out_e = leave : 0;
TRUE : neare;
esac;
next(nearw) := case
out_w = arrive : 1;
out_w = leave : 0;
TRUE : nearw;
esac;
next(east) := case
neare = 0 : red;
neare = 1 & west = red : green;
TRUE : east;
esac;
next(west) := case
nearw = 0 : red;
nearw = 1 & east = red & neare != 1 : green;
TRUE : west;
esac;
DEFINE
signal_w := west;
signal_e := east;
-- to test
MODULE WestTrainMonitor(out_w, out_e, signal_w)
VAR
state : {0,1,2,3};
ASSIGN
init(state) := 0;
next(state) := case
state = 0 & out_w = arrive : 1;
-- state = 0 : 0;
state = 1 & signal_w != green & out_e = leave : 2;
state = 1 & signal_w = green : 0;
-- state = 1 : 1;
state = 2 & signal_w != green & out_e = leave : 3;
state = 2 & signal_w = green : 0;
-- state = 2 : 2;
-- state = 3 : 3;
TRUE : state;
esac;
MODULE main
-- Composition of train_W, train_E and controller
VAR
train_w : train(contr.signal_w);
train_e : train(contr.signal_e);
contr : controller(train_w.out, train_e.out);
wtm : WestTrainMonitor(train_w.out, train_e.out, contr.signal_w);
INVARSPEC !(train_w.mode = bridge & train_e.mode = bridge);
INVARSPEC !(wtm.state = 3);

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MODULE main
-- Model of the switch
IVAR
press : boolean;
VAR
mode : {on, off};
x : 0..15;
ASSIGN
init(mode) := off;
next(mode) := case
mode = off & press : on;
mode = on & (press | x >= 10) : off;
TRUE : mode;
esac;
init(x) := 0;
next(x) := case
mode = on & next(mode) = off : 0;
mode = on & x < 10 : x + 1;
TRUE : x;
esac;
INVARSPEC x <= 10;
INVARSPEC mode = off -> x = 0;
INVARSPEC x < 10;
INVARSPEC mode = off;